1. Field of the Invention
The present invention is related to an internal supply voltage generator for a delay locked loop (DLL) circuit, and more particularly, to an internal supply voltage generator for a delay locked loop circuit, capable of preventing a voltage supplied to the DLL circuit by a circuit operation from lowering, during entering time from a power down period to other periods.
2. Discussion of Related Art
A delay locked loop DLL circuit receives a clock signal inputted from the external of a system and identifies an internal clock signal necessary in a system to a synchronization of a clock signal inputted from the external. This device supplying a driving voltage to the DLL is an internal supply voltage generator for the DLL circuit (hereinafter, referring as to a VDLL supply voltage generator).
FIG. 1 is a circuit diagram illustrating structures and operations of the internal supply voltage generator for the DLL circuit according to the conventional art.
Referring to FIG. 1, a VDLL supply voltage generator 110 supplying a supply voltage VDLL to a delay locked loop 120 generates the supply voltage VDLL by means of a reference voltage VREF, and is comprised of a comparator 111 and a switching device P111. Here, the reference voltage VREF is inputted to a first input terminal of the comparator 111, and the switching device P111 outputs an external supply voltage VDD as the supply voltage VDLL of the delay locked loop 120 by an analog-type operation, according to an output signal of the comparator 111. During this, the voltage switched by the switching device is inputted to a second input terminal of the comparator 111 and thus the reference voltage VREF and the supply voltage VDLL are identical by a feedback of the supply voltage VDLL and the analog-type operation.
On the other side, the delay locked loop 120 is operated by a power down signal PWRDN. The power down signal PWRDN is generated to a high level signal when its entering to a power down period is detected according to a clock enable signal CKE, and thus the delay locked loop 120 is stopped for an operation in the power down period according to the power down signal PWRDN, to minimize power consumption. While this, a lock information is latched and stored in the delay locked loop 120 before entering to the power down period.
As aforementioned, when the delay locked loop 12 is not operated in the power down period, there is no power consumption and then the supply voltage VDLL is risen. The rising of the supply voltage VDLL is dependant on a reacting speed of the VDLL supply voltage generator 110. When the reacting speed is fast, a width of the rising is narrow, while the width of the rising is wide when the reacting speed is slow.
In case of exiting the power down period, the power down signal PWRDN becomes low level, and the delay locked loop 120 is operated thereby. Here, the supply voltage VDLL is transiently used, which leads a level of the supply voltage VDLL to be lowered. Accordingly, the lowering rate of the supply voltage VDLL is decided according to the reacting speed of the VDLL power source generator 110 and degree of using a unit delay before the power down period.
In general, the reacting speed of the VDLL power source generator 110 is not fast. This is for preventing a fluctuation phenomenon of the supply voltage VDLL by a fast reacting speed from being generating.
As described above, if the reacting speed of the VDLL power source generator 110 is low and a transient falling speed is faster, it causes a problem that an output data access time from Clk tAC is outputted for a next read command with a delay.